A Software Tool to Detect Race and Deadlock Conditions Caused by Leakage in Speed-Independent Circuits

摘要

Asynchronous circuit designers mainly rely upon the timing relationship between gates to judge the correctness of their designs. They rarely consider the operating conditions, technology node features, and variations. Leakage current is one of the device properties that can cause indeterministic behavior in any circuit, especially asynchronous ones. For instance, leakage can change the state of flip-flips and registers or can discharge precharged bit-lines. These conditions can lead to deadlock or race conditions in asynchronous circuits, particularly speed-independent (SI) circuits. Unfortunately, existing asynchronous circuit design tools do not consider this issue during the design and testing phase. Therefore, it is the aim of this research to eliminate this gap. This paper proposes a new software tool that is capable of detecting race and deadlock conditions caused by leakage current in speed-independent circuits. The tool was developed in OCEAN, so it can be easily integrated with Spectre Circuit Simulator. The tool was tested on a number of SI circuits from literature, and results demonstrating the need for such a tool were obtained.