Low Cost Concurrent Error Masking Using Approximate Logic Circuits

摘要

With technology scaling, logical errors arising due to single-event upsets and timing errors arising due to dynamic variability effects are increasing in logic circuits. Existing techniques for online resilience to logical and timing errors are limited to detection of errors, and often result in significant performance penalty and high area/power overhead. This paper proposes approximate logic circuits as a design approach for low cost concurrent error masking. An approximate logic circuit predicts the value of the outputs of a given logic circuit for a specified portion of the input space, and can indicate uncertainty about the outputs over the rest of the input space. Using portions of the input space that are most vulnerable to errors as the specified input space, we show that approximate logic circuits can be used to provide low overhead concurrent error masking support for a given logic circuit. We describe efficient algorithms for synthesizing approximate circuits for concurrent error masking of logical and timing errors. Results indicate that concurrent error masking based on approximate logic circuits can mask 88% of targeted logical errors for 34% area overhead and 17% power overhead, 100% timing errors on all timing paths within 10% of the critical path delay for 23% area overhead and 8% power overhead, and 100% timing errors on all timing paths within 20% of the critical path delay for 42% area overhead and 26% power overhead.