As CMOS scaling continues, manufacturing costs increase substantially in part due to the challenges of subwavelength lithography. Alternative manufacturing methods that are proposed to enable affordable scaling require extreme layout regularity. Since modern systems are embedding increasing amounts of memory, constructing SRAM circuits efficiently from extremely regular patterns is of utmost importance. Further; robust SRAM design is becoming more challenging due to high random variability in nanoscale processes. Low-cost layout fabrics and variation-tolerant SRAM circuit techniques must be jointly explored to determine the optimal design/manufacturing strategy for affordable scaling.;This dissertation proposes a framework to systematically explore the fabric-circuit design space for the SRAM bitcell. The framework integrates performance models for various fabric-circuit solutions with an effective design space exploration strategy. Efficient statistical methods are used to accelerate SRAM parametric failure analysis. The design space of a given fabric-circuit solution, which is reduced due to extreme layout regularity, is exhaustively searched for pareto-optimal designs. The exhaustive exploration is accelerated via subsampling of the design space and highly parallelized design evaluations. The pareto-optimal fronts are used to compare various fabric-circuit solutions.;As a demonstration, the framework is used to explore the bitcell design space in a 45nm SOI process. This study considers two low-cost regular fabrics, each with specific regularity constraints for the diffusion layer, and various circuit solutions, including 6T and 8T topologies and a read/write assist technique. The results show that the 6T topologies cannot achieve acceptable parametric yields without using read/write assist. The 8T topology emerges as the optimal circuit solution in case the design cost of assist circuits is not affordable. The assisted 6T cells can be mapped onto the low-cost fabrics more efficiently than the ST cell unless the speed and yield requirements are extremely demanding. Non-gridded diffusion patterning improves cell area and leakage power by 10--25% and 2--16%, respectively, for the considered circuit solutions.;The area comparisons demonstrated in this experiment are strongly dependent on the extent of the pushed rules for a gridded design. To validate the area comparisons, prototype 8T bitcells were implemented using the pushed rules that are assumed by the area models. The lithography simulations of cell arrays and silicon measurements confirmed the viability of the pushed rules. The bitcell constructed from non-gridded diffusion patterns is 14% smaller than the bitcell constructed from gridded diffusion patterns, as predicted by the area models. 16 Kb arrays, including all the peripheral logic, were constructed from these bitcells to demonstrate and compare the array efficiency of the low-cost regular fabrics. Both fabrics achieve the same array efficiency of 76% when the decoder and control blocks are excluded. When those blocks are included, the fabric with gridded diffusion attains 58% array efficiency. Silicon measurements demonstrate that two distinctive regularity constraints on the diffusion layer do not lead to any significant difference in array speed and leakage.
展开▼
