Short-circuit power dissipation estimation for CMOS logic gates

摘要

Short-circuit power dissipation contributes significantly to the overall power dissipation in ICs. A new formula has been developed for the estimation of short-circuit power dissipation in CMOS logic gates based on the α-power law model that includes velocity saturation effects of short channel MOSFETs. A technique is developed for the measurement of short-circuit current and power dissipation of CMOS logic gates for use in circuit simulation. SPICE simulation results show that the new formula is significantly more accurate than existing formulae