A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time src='/images/tex/16713.gif' alt='Sigma Delta '> ADC for a Digital Closed-Loop Class-D Amplifier

摘要

This paper presents a continuous-time third-order modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range and 72-dB peak signal-to-noise and distortion ratio . The active-RC implementation allows the 1.1-V modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering.