A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time #x03A3;#x0394; ADC for a digital closed-loop class-D amplifier

摘要

This paper presents a continuous-time 3^rd order ΣΔ modulator implemented in 40-nm CMOS technology for closing the feedback loop of a digital class-D audio amplifier. The proposed ΣΔ A/D converter consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB DR and 72-dB peak SNDR. The active-RC implementation allows the 1.1-V ΣΔ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees 3^rd order anti-aliasing filtering.