首页> 外文期刊>IEEE transactions on circuits and systems . I , Regular papers >Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits – Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs
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Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits – Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs

机译:FD-SOI CMOS Body输入模拟电路的增强线性 - 应用于电压控制的环形振荡器和基于频率的ΣΔADC

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This paper investigates the use of the body terminal of MOS transistors to improve the linearity of some key circuits used to implement analog and mixed-signal circuits integrated in Fully Depleted Silicon on Insulator (FD-SOI) CMOS. This technology allows to increase the body factor with respect to conventional (bulk) CMOS processes. This effect is analyzed in basic analog building blocks -such as switches, simple-stage transconductors and Voltage-Controlled Ring Oscillators (VCROs). Approximated expressions are derived for the nonlinear characteristics and harmonic distortion of some of these circuits. As an application, transistor-level simulations of two VCRO-based Sigma Delta modulators designed in a 28-nm FD-SOI CMOS technology are shown in order to demonstrate the benefits of the presented techniques.
机译:本文调查了MOS晶体管的主体端子,以改善用于实现集成在绝缘体(FD-SOI)CMOS上完全耗尽的硅中集成的模拟和混合信号电路的一些关键电路的线性。该技术允许增加传统(批量)CMOS过程的身体因素。在基本模拟构建块-SUCH中分析这种效果作为开关,简单级超导电块和电压控制环振荡器(Vcros)。近似表达式用于一些这些电路的非线性特性和谐波失真。作为应用,示出了在28nm FD-SOI CMOS技术中设计的基于两个VCRO的Sigma Delta调制器的晶体管级模拟,以证明所提出的技术的益处。

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