Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis

摘要

State-of-the-art design dependent ring oscillators (DDROs) aim to evaluate the timing variability of critical paths due to process, temperature, and voltage (PVT) fluctuations by matching their delay sensitivities. In this paper, a novel concept to synthesize DDROs is introduced, where the objective of the synthesis is to match the delays instead of delay sensitivities of critical paths. Such delay-tracking based DDROs can be built using static timing analysis (STA) to characterize delays, which makes this approach applicable to large-scale industrial designs. Moreover, a novel heuristic algorithm is developed which reduces the complexity of the optimization problem in contrast to direct solvers. Furthermore, new methods to characterize delays of tiles, the building blocks of DDROs, are described. Simulation results are presented for an industrial design in a sub-40 nm technology node.