Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs

摘要

Sense amplifier (SA) input-referred offset often dictates the minimum required differential input (Delta VBL-min) and is an important factor in realizing low-voltage static random access memories. This paper presents a HYbrid latch-type Sense Amplifier (HYSA-QZ), where the bitline signals are supplied to multiple internal nodes to significantly reduce Delta VBL-min. A 65-nm CMOS test chip with arrays of the HYSA-QZ, two intermediate formulations of the HYSA-QZ, conventional current latch SA (CLSA), and conventional voltage latch SA (VLSA) were fabricated. Measurements over 5120 SAs of each type show that the HYSA-QZ implemented with regular-V-T transistors require 50.0%, and 22.8% lower Delta VBL-min with 6.5% (or 4.5%) and 30.7% (or 18.8%) of total gate (or layout) area overhead compared to CLSA and VLSA at 0.4 V, respectively. Iso-gate-area offset improvement was substantiated with Pelgrom's mismatch model, where the HYSA-QZ with regular-V-T transistors showed 46.6% and 7.7% improvements in measured standard deviation of offset distribution compared with CLSA and VLSA, respectively. Measured Delta VBL-min for the HYSA-QZ remains stable and low over a temperature range from 0 degrees C to 75 degrees C at 0.4 V. Moreover, an additional 13.0% reduction in Delta VBL-min was measured in the HYSA-QZ when using low-V-T transistors. Finally, the HYSA-QZ operates reliably at VDD-min of 260 mV in 25 degrees C.