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Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology

机译:用于三栅极FinFET技术的混合失调补偿锁存型读出放大器

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摘要

In this paper, a novel offset compensated latch-type sense amplifier consisting of hybrid (current & voltage) sensing operation is proposed for SRAMs. The offset compensation circuitry of the proposed sense amplifier includes FET based capacitors and current injection circuitry (CIC) for compensation against V-T mismatch of critical transistor pairs. The proposed amplifier does not cause extra overhead in SRAM access latency. The functionality of the proposed tri-gated FinFET sense amplifier in 20 nm technology is verified using 3D TCAD tool and its efficacy against V-T variability is tested with the help of HSPICE simulations. Reliability and performance characteristics of the proposed sense amplifier are compared with recently reported capacitor-based offset compensated sense amplifier (OCSA) and the conventional current-latched sense amplifier (CLSA). The proposed sense amplifier achieves 7.58% and 26.38% higher yield compared to OCSA and CLSA, respectively. In this study, the V-T mismatch in all critical transistor pairs of the sense amplifier was introduced simultaneously. The proposed amplifier outperforms OCSA and CLSA in the following: (i) 1.11 and 5.02 times higher offset tolerance, (ii) 1.66 and 2.66 times lower bit-line differential voltage (Delta V-in) to achieve target yield of 90%, and (iii) 16.84% and 52.94% lower standard deviation in sensing delay during read-0 operation due to higher offset tolerance. Effect of V(DD)scaling on yield and performance of various sense amplifiers is also evaluated. Under iso-area condition, the proposed sense amplifier exhibits 17.10% higher yield and x 2.55 higher offset tolerance in comparison with CLSA.
机译:在本文中,针对SRAM,提出了一种由混合(电流和电压)感测操作组成的新型失调补偿锁存型感测放大器。所提出的读出放大器的偏移补偿电路包括基于FET的电容器和电流注入电路(CIC),用于补偿关键晶体管对的V-T不匹配。拟议的放大器不会在SRAM访问延迟中造成额外的开销。使用3D TCAD工具验证了拟议的20纳米技术三栅极FinFET感应放大器的功能,并借助HSPICE仿真测试了其针对V-T可变性的功效。将所提出的读出放大器的可靠性和性能特性与最近报道的基于电容器的失调补偿读出放大器(OCSA)和常规电流锁存读出放大器(CLSA)进行了比较。与OCSA和CLSA相比,拟议的读出放大器可分别提高7.58%和26.38%的良率。在这项研究中,同时引入了读出放大器的所有关键晶体管对中的V-T不匹配。拟议的放大器在以下方面优于OCSA和CLSA:(i)偏移容限高1.11和5.02倍,(ii)位线差分电压(Delta V-in)低1.66和2.66倍,以达到90%的目标良率,以及(iii)由于较高的偏移容限,因此在read-0操作期间,检测延迟的标准偏差分别降低了16.84%和52.94%。还评估了V(DD)缩放对各种读出放大器的良率和性能的影响。在等面积条件下,与CLSA相比,拟议的读出放大器具有高17.10%的良率和2.55倍的偏移容差。

著录项

  • 来源
    《Integration》 |2018年第6期|258-269|共12页
  • 作者单位

    DD Univ, Dept Elect & Commun, Nadiad 387001, Gujarat, India;

    DD Univ, Dept Elect & Commun, Nadiad 387001, Gujarat, India;

    Vishwakarma Govt Engn Coll, Dept Elect & Commun, Chandkheda, Gujarat, India;

    DD Univ, Dept Elect & Commun, Nadiad 387001, Gujarat, India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Sense amplifier; FinFET; Offset tolerance; SRAM;

    机译:读出放大器;FinFET;偏移容差;SRAM;

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