Structured Design Methodology to Achieve a High SNR Electrical Impedance Tomography

摘要

In this paper, we present amethodology for designing the main circuit building blocks of an electrical impedance tomography (EIT) system. In particular, we derive equations that map system-level EIT specifications to the performance requirements of each circuit block. We also review the circuit architectures that are best suited for meeting a given set of performance requirements. Our proposed design methodology is focused on maximizing the EIT system's signal-to-noise ratio while minimizing total power consumption.