Integrated Circuit for High SNR Electrical Impedance Tomography

摘要

Electrical impedance tomography (EIT) is a promising technology for health telemonitoring devices because it is radiation-free, highly specific, affordable, and miniaturizable. Portable EIT imaging is required to have a wide dynamic range, utilize the least amount of power possible, and collect data rapidly while covering a wide frequency range.;In this work, the focus is on the development of the EIT system in two main areas: 1) a procedural design that relates the circuit specification of every individual block to a top-level EIT system requirement, and 2) design and implementation of a wide-bandwidth, fast, high signal-to-noise ratio (SNR), low-power EIT front-end.;In the first part of this research, the EIT chain is studied and equations are derived to formulate the design of each individual block, in order to bridge the gap between EIT system-level specifications and circuit design requirements.;In the second part, two different application-specific integrated circuits (ASICs) for the front-end of the EIT system are designed and implemented, where the second generation addresses the shortcomings of the first generation, as follows:;In the first version, an EIT front-end with a successive-approximation-register (SAR) ADC is developed. The read-out chain comprises a programmable-gain instrumentation amplifier (IA), an analog-to-digital converter (ADC) driver, and a hybrid resistive-capacitive (R-C) SAR ADC. The read-out channel is fabricated in a 0.18 mum CMOS technology. This is the first ASIC front-end for EIT that covers a wide range of frequencies from 100 Hz up to 10 MHz. The chain maintains an SNR between 68 and 56 dB and consumes between 6.9 mW and 21.8 mW based on its operating frequency. In this design, the power consumption of the chain for input frequencies higher than 3.5 kHz is fixed and equal to 21.8 mW.;To further improve the performance of the chain and reduce the power consumption, a fully power-adaptive chain with a dual-DAC hybrid R-C SAR ADC is implemented in a 0.18 mum CMOS technology and constitutes the second version. The chain covers frequencies ranging from 100 Hz up to 10 MHz. The total measured power consumption of the read-out chain ranges from 2.1 mW to 21.7 mW, while maintaining an SNR between 81 and 65 dB. The power consumption of the chain in this design increases with the input frequency in an almost linear fashion, which results in a significant reduction in power expenditure compared to the previous generation.