Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification

摘要

Functional verification is widely recognized as the bottleneck of the hardware design cycle. With the ever-growing demand for greater performance and faster time to market, coupled with the exponential growth in hardware size, verification has become increasingly difficult. Although formal methods such as model checking and theorem proving have resulted in noticeable progress, these approaches apply only to the verification of relatively small design blocks or to very focused verification goals. In current industrial practice, simulationbased techniques play a major role in the functional verification of microprocessors. The recent emergence of hardware verification languages and comprehensive environments designed to automate the functional verification process has significantly affected simulation-based technology. Engineers typically use these environments to verify ASICs, SoCs, and unit-level components in a processor. Using such environments to verify large processors (x86, PowerPC, and so on) still requires significant effort. Current industry practice is to use separate, automatic, random stimuli generators for processor-and multiprocessor-level verification. The generated stimuli, usually in the form of test programs, trigger architecture and microarchitecture events defined by a verification plan. In general, test programs must meet the validity requirement (the tests' embedded behavior should conform to the targeted design's specification) and the quality requirement (the tests should expand the targeted design's coverage and increase the probability of bug discovery). The generator can produce many distinct, well-distributed test program instances that comply with user requests. Numerous random selections made during generation achieve the variation among different instances.