Generation of design verification tests from behavioral VHDLprograms using path enumeration and constraint programming

摘要

A method for generation of design verification tests fromnbehavior-level VHDL programs is presented. The method generates stimulinto execute desired control-flow paths in the given VHDL program. Thisnmethod is based on path enumeration, constraint generation andnconstraint solving techniques that have been traditionally used fornsoftware testing. Behavioral VHDL programs contain multiplencommunicating processes, signal assignment statements, and waitnstatements which are not found in traditional software programmingnlanguages. Our model of constraint generation is specifically developednfor VHDL programs with such constructs. Control-flow paths for whichndesign verification tests are desired are specified through certainnannotations attached to the control statements in the VHDL programs.nThese annotations are used to enumerate the desired paths. Eachnenumerated path is translated into a set of mathematical constraintsncorresponding to the statements in the path. Methods for generatingnconstraint variables corresponding to various types of carriers in VHDLnand for mapping various VHDL statements into mathematical relationshipsnamong these constraint variables are developed. These methods treatnspatial and temporal incarnations of VHDL carriers as unique constraintnvariables thereby preserving the semantics of the behavioral VHDLnprograms. Constraints are generated in the constraint programmingnlanguage CLP(R) and are solved using the CLP(R) system. A solution tonthe set of constraints so generated yields a design verification testnsequence which can be applied for executing the corresponding controlnpath when the design is simulated. If no solution exists, then itnimplies that the corresponding path can never be executed. Experimentalnstudies pertaining to the quality of path coverage and fault coverage ofnthe verification tests are presented