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Finite element modeling of dislocation reduction in GaAs and InP single crystals grown from the VGF process

机译:VGF工艺生长的GaAs和InP单晶中位错减少的有限元建模

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Dislocations in gallium arsenide (GaAs) and indium phosphide (InP) crystals are generated by thermal stresses induced during their solidification process of crystal growth. High dislocation density in these crystals will reduce the performance and reliability of the GaAs- and InP-based microelectronic and photonic devices/circuits. It has been known that doping impurity atoms into GaAs and InP crystals during their solidification process can significantly reduce dislocation densities generated in these crystals. A viscoplastic constitutive equation that couples a microscopic dislocation density and impurity atoms with a macroscopic plastic deformation is employed in a transient finite element model for predicting the dislocation density generated in the undoped and doped GaAs and InP crystals grown by the vertical gradient freeze (VGF) process. The effects of crystal growth parameters (i.e., imposed temperature gradient, crystal diameter, and crystal growth rate) on dislocation generation are also investigated. The numerical results show that doping impurity can significantly reduce the dislocation density generated in these crystals. It also shows that dislocation density reduces drastically as the crystal diameter and imposed temperature gradient decrease, but the crystal growth rate has almost no effect on dislocation generation in these crystals.
机译:砷化镓(GaAs)和磷化铟(InP)晶体中的位错是由晶体生长的凝固过程中产生的热应力产生的。这些晶体中的高位错密度将降低基于GaAs和InP的微电子和光子器件/电路的性能和可靠性。众所周知,在其凝固过程中将杂质原子掺杂到GaAs和InP晶体中可以显着降低这些晶体中产生的位错密度。在瞬态有限元模型中,采用将微观位错密度和杂质原子与宏观塑性变形结合起来的粘塑性本构方程,用于预测由垂直梯度冻结(VGF)生长的未掺杂和掺杂的GaAs和InP晶体中产生的位错密度。处理。还研究了晶体生长参数(即,施加的温度梯度,晶体直径和晶体生长速率)对位错产生的影响。数值结果表明,掺杂杂质可以显着降低这些晶体中产生的位错密度。它还表明,随着晶体直径和施加的温度梯度降低,位错密度急剧降低,但是晶体生长速率几乎对这些晶体中的位错产生没有影响。

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