Techniques for fabrication of wafer scale interconnections in multichip packages

摘要

Wafer-scale hybrid packaging (WSHP), multichip modules (MCM), high-density interconnect (HDI), thin-film multilayer (TFML) packaging, and advanced VLSI packaging (AVP) are different terms used to refer to an approach for fabricating chip-to-chip connections using semiconductor technology. However, persistent yield problems have made successful scale-up of the technology to full-sized, system-oriented wafer-scale packages difficult. Most of these problems can be traced to stress resulting from the different thermal properties of the various materials used in fabrication and the high-temperature processing steps involved. The authors explore use of focused-electron-beam and ion-beam repair strategies for coping with residual faults in a model high-yield liftoff process for fabricating wafer-scale interconnections in multichip packages.