JFET/SOS devices. II. Gamma-radiation-induced effects

摘要

For pt.I see ibid., vol.35, no.3, p.353-8 (1988). Enhancement-mode and depletion-mode JFETs have been fabricated on silicon-on-sapphire (SOS) substrates. When these devices are irradiated under bias with a /sup 60/Co source, their drain currents increase, and their threshold voltages shift in such a way that the devices become more difficult to pinch off. These effects can be explained by positive charge trapping at the silicon-sapphire interface. Gate-to-drain leakage currents also increase, and can be traced to interface effects at the gate edges rather than to the passivating oxide. These effects were studied as a function of dose rate and postirradiation annealing. Deep-level transient spectroscopy (DLTS) was performed prior to and following both irradiation and anneal on both the gate-drain and gate-source p-n junctions. DLTS trap bands were observed whose characteristics depended on the depth of the depletion layer and on the total gamma dose received. The DLTS spectra suggest that a continuum of levels is responsible for the bands, and that the emission kinetics are influenced by band bending at the Si-sapphire interface. The major bands correspond in temperature with steps in capacitance-temperature curves.