JFET/SOS devices. I. Transistor characteristics and modeling results

摘要

A process for fabricating n-channel junction field-effect transistors (JFET) on silicon-on-sapphire (SOS) wafers has been developed. Both enhancement-mode and depletion-mode transistors were fabricated, and their characteristics were measured and are discussed. All dopants were ion implanted. A number of calculational tools, including SUPREME-II, were used to estimate the junction depths and the mode of device operation. Calculations were also performed using PISCES-II, a device-modeling program that predicts operating characteristics. The mobilities used in these calculations were reduced from bulk silicon values to account for the degraded mobility of the SOS material. The mobility of the SOS material was measured using capacitance-voltage and conductance-voltage techniques on a device with a long gate. A decrease in mobility with decreasing temperature is deduced from device behavior at low temperatures.