Narrow-width effects of shallow trench-isolated CMOS with n/sup +/-polysilicon gate

摘要

Narrow-width effects are discussed of n- and p-MOSFETs with shallow trench isolation. MOSFETs with n/sup +/-polysilicon gates were fabricated down to channel widths of 0.5 mu m by using a novel planarization process with an etch stop. The threshold behavior is characterized as a function of both the sidewall-implanted boron and the three dimensional process/device simulations. The trench-isolated n-MOSFET shows the narrow-width effect with excess boron doses implanted in the sidewalls. It is found that the lateral diffusion of sidewall-implanted boron induces enhancement of the edge current although the devices show narrow-width effects. The trench-isolated p-MOSFETs show narrow-width effects with the buried-channel mode and the inverse-narrow width effect when surface channel conditions dominate at threshold. It is found that the narrow-width effect of p-MOSFETs strongly depends on the threshold adjustment by means of counter doping.