An all-electrical floating-gate transmission line model technique for measuring source resistance in heterostructure field-effect transistors

摘要

A new technique for determining the parasitic source resistance in heterostructure field-effect transistors (HFETs) is presented. The new technique is an improvement of the floating-gate transmission line model and uses purely electrical measurements; there is no need to determine any critical lengths optically or by scanning electron microscopy. The technique is demonstrated in In/sub 0.52/Al/sub 0.48/As/sup +/-In/sub 0.53/Ga/sub 0.47/As metal-insulator-doped semiconductor field-effect transistors (MIDFETs). The new technique holds great promise for automated measurements of source resistance in a manufacturing environment.