An improved method to correlate measured circuit speed with simulation (CMOS gate arrays)

摘要

The relationship between the measured propagation delay of elementary circuits and the values obtained by circuit SPICE modeling was studied. Systematic and random variations of L/sub eff/ of the actual circuit from the modeled values L/sub eff/, which were extracted from separate test devices, were identified as a major source of error. The error was significantly reduced by an improved method to obtain the values of L/sub eff/ within the logic circuits, thus permitting accurate circuit performance modeling and the required technology optimization.