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首页> 外文期刊>IEEE Transactions on Electron Devices >Optimum DMOS cell doping profiles for high-voltage discrete and integrated device technologies
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Optimum DMOS cell doping profiles for high-voltage discrete and integrated device technologies

机译:适用于高压分立和集成器件技术的最佳DMOS单元掺杂分布

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摘要

It is shown that the implementation and activation sequences of B and As result in significant variations in the contact resistance and p-base sheet resistance beneath the n/sup +/-source diffusion of a DMOSFET cell. For identical process parameters, the contact resistance of As-doped n/sup +/ silicon was significantly improved when high-dose B was implanted due to higher As surface concentration. The SUPREM III process modeling results were found to be in qualitative agreement with the measured spreading resistance profiles and the discrepancies could be attributed to larger high-temperature diffusion constants used in SUPREM III and the coupled As-B diffusion/activation effects that are not accounted for in process modeling. The experimental results are discussed within the framework of fabricating high-performance DMOSFET cells and CMOS high-voltage devices on the same chip for discrete and smart-power applications.
机译:结果表明,在DMOSFET单元的n / sup +/-源极扩散以下,B和As的实施和激活顺序会导致接触电阻和p基片电阻的显着变化。对于相同的工艺参数,由于较高的As表面浓度,当注入大剂量B时,掺杂As的n / sup + //硅的接触电阻显着提高。发现SUPREM III的过程建模结果与测得的扩展电阻曲线在质量上一致,差异可能归因于SUPREM III中使用的较大的高温扩散常数以及未考虑的As-B耦合扩散/活化效应用于过程建模。实验结果是在同一芯片上制造高性能DMOSFET单元和CMOS高压器件的框架中讨论的,以用于分立和智能电源应用。

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