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Gate-oxide thickness dependence of hot-carrier-induced degradation in buried p-MOSFET's

机译:埋入p-MOSFET中热载流子引起的退化的栅极氧化物厚度依赖性

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The gate-oxide thickness dependence of hot-carrier-induced degradation in buried p-MOSFETs is described. The results reveal that the thinner gate oxide provides higher hot-carrier resistance even with high hot-electron generation. A significant improvement of the threshold voltage shift is obtained for a buried p-MOSFET with a thin gate oxide of 7 nm at a wide range of stress gate voltages. This effect is induced by a significantly different mechanism from that of n-MOSFETs. The mechanism is explained by using a numerical degradation simulation, which self-consistently includes the models for the hot-carrier transport in silicon, emission process, carrier behavior in the oxide, and carrier trapping. It is found that the degradation of the buried p-MOSFETs is characterized by the dynamics of the electron heating process during stress and the corresponding position of the trapped electrons.
机译:描述了掩埋p-MOSFET中热载流子引起的退化的栅极氧化物厚度依赖性。结果表明,即使在产生高热电子的情况下,较薄的栅极氧化物也具有较高的热载流子电阻。对于在宽的应力栅极电压范围内具有7 nm薄栅极氧化物的埋入式p-MOSFET,阈值电压漂移得到了显着改善。这种效应是由与n-MOSFET明显不同的机制引起的。通过使用数值退化仿真来解释该机理,该仿真自洽地包括硅中热载流子传输,发射过程,氧化物中的载流子行为和载流子捕获的模型。发现掩埋的p-MOSFET的退化的特征在于应力期间电子加热过程的动力学以及被俘获电子的相应位置。

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