How to reduce anomalous narrow channel effects in trench-bound buried-channel p-MOSFETs

摘要

The present invention relates to a method of fabricating a p-type metal oxide semiconductor field effect transistor (p-MOSFET) in a buried channel bounded by a trench used in dynamic random access memory (DRAM) technology, particularly with respect to device width. A method for reducing the abnormal sensitivity of the p-MOSFET of a channel. In one embodiment, the method comprises starting a low temperature annealing step with an inert gas after the deep phosphorus n-well implant step, before the boron buried channel implant and the 850 ° C. gate oxidation step. Optionally, the annealing step may be performed after the boron buried channel implantation, but before the 850 ° C. gate oxidation step. In another embodiment, the fast reverse oxidation (RTO) step can be replaced instead of the 850 ° C. gate oxidation step following the thick phosphorus n-well and boron buried channel implantation steps. Optionally, the 850 ° C. gate oxidation step may come before the RTO gate oxidation step.