A planar interconnection technology utilizing the selective deposition of tungsten-multilevel implementation

摘要

The increases in crosstalk disturbance, signal delay, and current density as interconnections are scaled have been examined through simulations. Interconnections will greatly degrade the performance of integrated circuits if the metal pitch is reduced to much below 2 mu m. An alternative to achieve the continuous demand in increasing the interconnection density is to add multiple layers of metallization. A tungsten interconnection technology, which inherently preserves a flat wafer surface, as well as providing frameless and stacked vias, has been demonstrated. Electrical characterization and limitations of the technology are discussed.