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Effect of rapid epitaxy in in situ phosphorus-doped polysilicon emitter on current-gain of bipolar transistors

机译:快速外延原位掺杂磷的多晶硅发射极对双极晶体管电流增益的影响

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The effect of rapid solid-phase epitaxy (SPE) on the current gain of in situ phosphorus-doped polysilicon-emitter (IDP) transistors has been evaluated, IDP technology is used to produce very-high-speed small-emitter bipolar transistors, which have very high current gain due to their hetero-emitter-like characteristics. The IDP film is deposited on a clean poly/mono-silicon surface, followed by rapid thermal annealing (RTA). The poly/mono interface was analyzed and the lattice image was observed by high-resolution transmission electron microscopy (TEM). The majority of the IDP transistors had poly/mono-silicon interfacial hetero-emitter-like characteristics and thus had high current gain. The remaining transistors, however, did not exhibit hetero-emitter-like characteristics due to SPE and thus the current gain was reduced. These results are well explained using an interfacial residual-stress model: rapid epitaxy occurs when the amorphous silicon film is annealed by RTA, which eliminates the interfacial residual stress and in turn the hetero-emitter-like characteristics.
机译:已经评估了快速固相外延(SPE)对原位掺杂磷的多晶硅发射极(IDP)晶体管的电流增益的影响,IDP技术用于生产超高速小发射极双极晶体管,由于具有类似异质发射极的特性,因此具有非常高的电流增益。将IDP膜沉积在干净的多晶硅/单晶硅表面上,然后进行快速热退火(RTA)。分析了poly / mono界面,并通过高分辨率透射电子显微镜(TEM)观察了晶格图像。大多数IDP晶体管具有类似于多晶硅/单晶硅异质结的特性,因此具有较高的电流增益。但是,由于SPE,其余晶体管没有表现出类似异质发射极的特性,因此电流增益降低了。使用界面残余应力模型可以很好地解释这些结果:当非晶硅膜通过RTA退火时,会发生快速外延,这消除了界面残余应力,进而消除了异质发射极特性。

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