A dynamic-threshold SOI device with a J-FET embedded source structure and a merged body-bias-control transistor. I. A J-FET embedded source structure properties

摘要

The floating-body effects in SOI CMOSFETs are fully suppressed by embedding a J-FET source structure immediately beneath the source/drain junction. The drain of the J-FET consists of a Schottky barrier diode; the holes generated in the body can easily be ejected into the source through the forward-biasing of this diode. The source-drain breakdown voltage and drain-induced barrier-lowering characteristics of this device are the same as those of a bulk device. With this structure, the body potential syncrhronously couples to the gate bias in the dynamic mode without potential hysteresis when the body-to-source resistance is properly designed. The inverter-chain delay time should be 45% of that of a bulk device operating at 1 V without an excess load.