From Wafer-Level Gate-Oxide Reliability Towards ESD Failures in Advanced CMOS Technologies

摘要

The impact of a short-term electrical overstress on dielectric reliability is thoroughly investigated using a dedicated experimental equipment for measurement times in the millisecond and microsecond range. Based on significant statistics, it is confirmed that the dielectric stress-induced damage is cumulative in nature. In addition, the voltage acceleration is shown to follow the power-law model towards the time range of electrostatic discharge and furthermore the breakdown statistics remain unchanged. These results justify the assessment of a short-term electrical overstress in advanced CMOS technologies by using a conventional reliability prediction methodology.