Short-Channel Characteristics of Self-Aligned $Pi$-Shaped Source/Drain Ultrathin SOI MOSFETs

摘要

A novel device architecture—the self-aligned $Pi$ -shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET—is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest degradation of the short-channel characteristics including drain-induced barrier lowering (DIBL) and subthreshold swing (SS), when compared with a traditional UTSOI-FET. This degradation occurs because the S/D-tied scheme introduces two additional pathways between the S/D regions and the silicon substrate, thereby reducing the gate''''s ability to control the channel. Yet, the results presented here show these negative effects to be reasonably small (e.g., $hbox{DIBL} ≪ hbox{90} hbox{mV/V}$ and $hbox{SS} ≪ hbox{100} hbox{mV/dec}$ ), whereas the positive effect of reduced self-induced heating is substantial and significantly improves device reliability.