Three-Dimensional Simulation of Dopant-Fluctuation-Induced Threshold Voltage Dispersion in Nonplanar MOS Structures Targeting Flash EEPROM Transistors

摘要

Threshold voltage $(V_{T})$ dispersion due to random discrete dopant fluctuation was simulated in recessed-channel, triple-gate, and saddle MOS structures, targeting future floating-gate memory cell transistor. All nonplanar structures showed improved $V_{T}$ dispersion characteristics, compared with the planar type by proper adjustment of the tunnel oxide structure and channel doping level. The recessed-channel showed a continuous improvement of $V_{T}$ dispersion with the channel area widening beyond a certain threshold recess depth. In triple-gate structure, a significant reduction in $V_{T}$ dispersion is shown possible primarily via the superior gate controllability. Among the nonplanar structures, the saddle structure yielded the lowest $V_{T}$ variation for a fixed target $V_{T}$ with the choice of moderate device parameters from the other structures.