Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET

摘要

We utilized a fully self-consistent quantum mechanical simulator based on the Contact Block Reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device on-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a ${bf SiO}_{2}$ gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.