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Device Design and Optimization Methodology for Leakage and Variability Reduction in Sub-45-nm FD/SOI SRAM

机译:低于45nm FD / SOI SRAM的漏电和降低可变性的器件设计和优化方法

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Ultrathin-body fully depleted silicon-on-insulator (UTB FD/SOI) devices have emerged as a possible candidate in sub-45-nm technologies and beyond. This paper analyzes leakage and stability of FD/SOI 6T SRAM cell and presents a device design and optimization strategy for low-power and stable SRAM applications. We show that large variability and asymmetry in threshold-voltage distribution due to random dopant fluctuation (RDF) significantly increase leakage spread and degrade stability of FD/SOI SRAM cell. We propose to optimize FD devices using thinner buried oxide (BOX) structure and lower body doping combined with negative back-bias or workfunction engineering in reducing the RDF effect. Our analysis shows that thinner BOX and cooptimization of body doping and back biasing are efficient in designing low-power and stable FD/SOI SRAM cell in sub-45-nm nodes.
机译:超薄型全耗尽型绝缘体上硅(UTB FD / SOI)器件已成为45纳米以下及以下技术的潜在候选者。本文分析了FD / SOI 6T SRAM单元的泄漏和稳定性,并提出了针对低功耗和稳定SRAM应用的器件设计和优化策略。我们表明,由于随机掺杂物波动(RDF)而导致的阈值电压分布中的较大变异性和不对称性显着增加了泄漏扩散并降低了FD / SOI SRAM单元的稳定性。我们建议使用更薄的掩埋氧化物(BOX)结构和下体掺杂结合负反向偏置或功函数工程来优化FD器件,以降低RDF效应。我们的分析表明,更薄的BOX以及体掺杂和背偏置的共优化可有效地设计低于45nm节点的低功耗且稳定的FD / SOI SRAM单元。

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