A Model of the Gate Capacitance of Surrounding Gate Transistors: Comparison With Double-Gate MOSFETs

摘要

In this work, we develop a comprehensive model of the total gate capacitance $(C_{G})$ of circular-cross-section surrounding gate transistors that accounts for both the insulator gate capacitance $(C_{rm ins})$ and the inversion capacitance $(C_{rm inv})$. The accuracy of the model is checked with the results obtained from the numerical simulation of the structure. Using this model, we compare the $C_{G}/C_{rm ins}$ ratio with that of double-gate (DG) transistors and study the degradation of the total gate capacitance of both devices as a function of the gate voltage and device size. It is shown that the $C_{G}/C_{rm ins}$ ratio is higher in DGs, particularly for very small devices.