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Circuit arrangement for functional inspection of power transistor, has evaluation device comparing measured gate-connection-capacitance with gate capacitance and outputting error signal in dependence of comparison
Circuit arrangement for functional inspection of power transistor, has evaluation device comparing measured gate-connection-capacitance with gate capacitance and outputting error signal in dependence of comparison
The arrangement has a control device (2) with a signal output that is connected to a gate (G) by a gate-connection contact (3g). A capacitance measuring device (6) measures a gate-connection-capacitance between the gate-connection contact and a power electrode-connection contact (3s). An evaluation device (8) compares the measured gate-connection-capacitance with a gate capacitance (Cg) and outputs an error signal in dependence of the comparison. An independent claim is also included for a method for functional inspection of power transistors.
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