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High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure

机译:具有p柱结构的高性能分栅增强型UMOSFET

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In this paper, a split-gate resurf stepped oxide (RSO) vertical UMOSFET with p-pillar under the ${rm p}^{+}$ plug region structure is proposed. The p-pillar could modulate the electric field of the drift region with the split-gate in 3-D and simultaneously brings electric field peaks at the sidewall junction between p-pillar and n-drift region. Thus the split-gate enhanced with p-pillar (SGEP) UMOS could increase the drift region doping concentration, reduce the on-state-specific resistance, and maintains the breakdown voltage as compared with the super junction and split-gate RSO UMOSs. Numerical simulation results show that the charge imbalance endurance of SGEP is also largely increased.
机译:在本文中,在<公式公式类型=“ inline”> $ {rm p} ^ {+} $ 塞区域结构。 p柱可以在3-D中使用分裂栅调节漂移区的电场,并同时在p柱和n漂移区之间的侧壁结处产生电场峰值。因此,与超结和分裂栅RSO UMOS相比,用p柱(SGEP)UMOS增强的分裂栅可以增加漂移区掺杂浓度,降低导通比电阻,并维持击穿电压。数值模拟结果表明,SGEP的电荷不平衡耐久性也大大提高。

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