$RC$ Performance Evaluation of Interconnect Architecture Options Beyond the 10-nm Logic Node

摘要

This paper summarizes the findings of an $RC$ performance modeling approach for evaluating various material and architecture options by which interconnect wires are incorporated onto integrated circuits. For the present dual-damascene structure, the grain boundary and surface scattering modes are identified as the top contributors to resistance degradation, along with the cross-sectional area consumed by the liner/barrier layers. Self-forming barriers, a technology that provides direct Cu-insulator interfaces, would quench surface scattering and provide larger cross-sectional area for the conductor in the wire. In addition, if engineered to be thinner than 1.5 nm, they would not negatively impact capacitance. This new architecture also allows for replacing low- $k$ dielectric fill with air-gap incorporation, further enhancing the capacitance component of the $RC$ delay. This proposed new scheme is shown to deliver the $RC$ -related performance metrics set by the International Technology Roadmap for Semiconductors. Other conductor possibilities, such as Co and W, are also evaluated along with subtractive metal processing options.