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High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

机译:高速,低功耗超深亚微米III-V非异质结隧道场效应晶体管

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Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, ${rm Si}{:}{rm Si}_{0.3}{rm Ge}_{0.7}$, Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length $({rm EOT}=2~{rm nm})$ and dielectric, ${rm HfO}_{2}$ at ${V}_{rm GS}=1~{rm V}$ and temperature of 300 K have ${I}_{{{rm ON}}}$ of 0.02–12.5 ${rm mA}/mu{rm m}$, $I_{{{rm ON}}}/I_{{{rm OFF}}}$ of $10^{5}hbox{--}10^{12}$, and subthreshold swing (average) of 16–74 mV/decade.
机译:隧道场效应晶体管(TFET)器件因具有良好的可扩展性而受到关注,并且其漏电流非常低。然而,它们遭受低导通电流和高阈值电压的困扰。在本文中,我们介绍了用于电路应用的III-V非异质结TFET(H-JLTFET)。本文阐述了III-V族与IV族半导体的异质结接口。通过实施异质结和带隙工程,我们发现即使在非常低的工作电压下,器件也可以以非常高的速度显着提高性能。由于不存在掺杂结,因此未来的缩放以及比硅中更高的载流子速度是可行的。 GaAs:Si,$ {rm Si} {:} {rm Si} _ {0.3} {rm Ge} _ {0.7} $,Si:InAs和GaAs:Ge,H-JLTFET接口,用于20 nm栅极长度$ ({rm EOT} = 2〜{rm nm})$和电介质,$ {rm HfO} _ {2} $ at $ {V} _ {rm GS} = 1〜{rm V} $,温度为300 K的$ {I} _ {{{{rm ON}}}} $ of 0.02–12.5 $ {rm mA} / mu {rm m} $,$ I _ {{{{rm ON}}}} / I _ {{{rm OFF} }} $$ 10 ^ {5} hbox {-} 10 ^ {12} $,阈值下摆幅(平均值)为16-74 mV /十倍。

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