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Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

机译:UTB SOI MOSFET中背栅对栅极感应的漏极泄漏和栅极电流的影响的建模

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摘要

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.
机译:提出了背栅偏压相关的栅致漏漏(GIDL)和超薄体(UTB)绝缘体上硅(SOI)MOSFET的栅极电流模型。根据实验数据,由于沟道/漏极结中的电场变化,GIDL电流取决于反向偏置。使用有效的栅极偏置作为阈值电压的偏移来对这种效应进行建模。还对背栅偏置相关的栅极电流进行了分析和建模。氧化物两端的电压和可用于隧穿的电荷是重要因素。在累积偏置条件下,栅极泄漏电流主要流经重叠区域,而在反向偏置条件下,电流从栅极流向沟道。背向偏置相关的GIDL模型和栅极电流模型均已实现到行业标准的紧凑型Berkeley短沟道IGFET模型无关的多栅极UTB SOI晶体管。该模型与实验数据吻合良好。

著录项

  • 来源
    《IEEE Transactions on Electron Devices》 |2017年第10期|3986-3990|共5页
  • 作者单位

    Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;

    Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;

    Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;

    Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;

    Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;

    Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;

    Macquarie University, Sydney, N.S.W., Australia;

    Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;

    Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Logic gates; MOSFET circuits; Tunneling; Leakage currents; Data models; MOSFET; Semiconductor device modeling;

    机译:逻辑门;MOSFET电路;隧道;漏电流;数据模型;MOSFET;半导体器件建模;

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