Optimization of implant anneals to improve transistor performance in a 0.15 /spl mu/m CMOS technology

摘要

The impact of including a rapid thermal anneal step after the extension implants is examined for a 0.15 /spl mu/m CMOS process. SIMS data will verify that shallower junctions can be obtained with only a single anneal cycle after the source-drain implants, implying that transient enhanced diffusion is minimal for this technology. Further, transistor data indicates that improved CMOS device performance can be obtained without the extension anneal cycle.