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Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface

机译:利用肖特基界面处的杂质隔离,优化金属源/漏SOI MOSFET的RF性能

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This letter presents a detailed investigation of the impact of dopant segregation (DS) on radio-frequency (RF) performance of p-type 110-nm undoped ultrathin-body Schottky-barrier (SB) silicon-on-insulator MOSFETs. It is shown that optimizing this dopant-segregated layer via careful control of the dopant concentration $(N_{rm SEG})$ and lateral extension $(L_{rm SEG})$ reduces the apparent potential barrier height at the Schottky junctions. This results in highly reduced source/drain (S/D) contact resistances, along with a peak $f_{T}$ value obtained at very low dc power consumption (45 $muhbox{W}/muhbox{m}$ at $V_{rm DS} = -hbox{2} hbox{V}$), which is very promising to address low-power low-voltage analog applications. Finally, the source resistance extracted from this RF study $(sim !!hbox{120} Omega cdotmuhbox{m})$ clearly demonstrates the ability of the DS SB S/D architecture to pursue the silicon roadmap beyond the 22-nm node.
机译:这封信详细介绍了掺杂剂隔离(DS)对p型110纳米无掺杂超薄肖特基势垒(SB)绝缘体上硅MOSFET的射频(RF)性能的影响。结果表明,通过仔细控制掺杂剂浓度$​​(N_ {rm SEG})$和横向延伸量$(L_ {rm SEG})$来优化该掺杂剂隔离层,可以降低肖特基结的表观势垒高度。这样可大大降低源/漏(S / D)接触电阻,以及在非常低的直流功耗下获得的峰值$ f_ {T} $值(在$ V_时为45 $ muhbox {W} / muhbox {m} $ {rm DS} = -hbox {2} hbox {V} $),这对于解决低功耗低压模拟应用非常有希望。最后,从此RF研究中提取的源电阻$(sim !! hbox {120} Omega cdotmuhbox {m})$清楚地证明了DS SB S / D架构具有超越22纳米节点的硅路线图的能力。

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