Realization of Ni Fully Silicided Gate on Vertical Silicon Nanowire MOSFETs for Adjusting Threshold Voltage $({V}_{T})$

摘要

A vertical Si nanowire (SiNW) gate-all-around n-type MOSFET integrated with Ni fully silicided gate is presented. Devices are fabricated with 100 nm gate length on vertical SiNWs with diameters down to 50 nm using fully CMOS compatible top-down approach. Tunability of the threshold voltage $(Delta V_{T} sim hbox{0.3} hbox{V})$, which is vital in nanowire devices to make them suitable for circuit integration, has been achieved without impacting other electrical parameters ( $SS < hbox{70} hbox{mV/dec}$, $DIBL < hbox{30} hbox{mV/V}$, and $I_{rm on}/I_{rm off} > hbox{10}^{7}$ ). In addition, $V_{T}$ dependence on nanowire diameter is studied. The results indicate that multiple $V_{T}$ required in logic circuits can be implemented through different nanowire diameters with the same doping conditions for all devices.