New Leakage Mechanism and Dielectric Breakdown Layer Detection in Metal-Nanocrystal-Embedded Dual-Layer Memory Gate Stack

摘要

We study the dielectric breakdown (BD) behaviors in MOS capacitor structures with metal-nanocrystal (NC)-embedded dual-layer $(hbox{SiO}_{2}/hbox{Al}_{2}hbox{O}_{3})$ gate stack. Using a unique stressing methodology of inducing a BD path in one of the two dielectric layers, the effect of BD in the blocking or tunnel oxide is assessed. The first layer to BD is determined based on the physics underlying the Coulomb charging energy in relation to thermal energy gained by electrons at low voltage and in the very low temperature regime ranging from 11 K to 300 K. The established methodology to detect the BD layer in an NC-embedded dual-layer dielectric can be applied for any bilayered NC system, regardless of the thickness of the tunnel and blocking oxide layer. It is noted that BD in $ hbox{SiO}_{2}$ leads to lateral charging/discharging among NCs, while, in $hbox{Al}_{2}hbox{O}_{3}$, it leads to spontaneous BD of bilayer gate stacks owing to high localized trap generation rate around the high- $kappa$ dielectric grain boundary and local electric field enhancement in the vicinity of metal NCs.