Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform

摘要

In this letter, we investigate the effect of device and layout parasitics on circuit performance of vertical nanowire (VNW) CMOS technology. We evaluate the effect of source–drain extension $(S/D_{rm ext})$ scaling and device asymmetry on device and circuit performances for 15 nm VNW CMOS. It is seen that, due to reduced series resistance, circuit delay continues to improve with $S/D_{rm ext}$ down to 10 nm, despite increased parasitic capacitances. Also, we show that asymmetry between top and bottom electrodes plays a strong role in determining circuit delay, while layout-dependent parasitics are of secondary importance. The results show that delay is increased by 65% with top electrode as source, which is attributed to increase in series resistance and gate–drain overlap capacitances. The comparison of VNW and FinFET CMOS shows nearly 40% delay reduction, highlighting excellent potential of VNW CMOS for 15 nm and below technology nodes.