首页> 外文期刊>Electron Device Letters, IEEE >Demonstration of Normally-Off Recess-Gated AlGaN/GaN MOSFET Using GaN Cap Layer as Recess Mask
【24h】

Demonstration of Normally-Off Recess-Gated AlGaN/GaN MOSFET Using GaN Cap Layer as Recess Mask

机译:使用GaN盖层作为凹槽掩模演示常关凹槽栅极式AlGaN / GaN MOSFET

获取原文
获取原文并翻译 | 示例

摘要

Based on our proposed self-terminating gate recess etching technique, normally-off recess-gated AlGaN/GaN MOSFET has been demonstrated with a novel method using GaN cap layer (CL) as recess mask, which, as a result, simplifies the device fabrication process and lowers the fabrication cost. The GaN CL is capable of acting as an effective recess mask for the gate recess process, which includes a thermal oxidation for 45 min at 650 °C followed by 4-min etching in potassium hydroxide (KOH) at 70 °C. After gate recess process, no obvious change is observed in terms of the surface morphology of the GaN CL, the contact resistance of the Ohmic contact formed directly on the GaN CL as well as the sheet resistance of the two-dimensional electron gas (2-DEG) channel layer under the GaN CL. The fabricated device exhibits a threshold voltage ( as high as 5 V, a maximum drain current ( of mA/mm, a high on/off current ratio of together with a low forward gate leakage current of mA/mm. Meanwhile, the OFF-state breakdown voltage ( of the device with gate-drain distance of 6 m is 450 V.
机译:基于我们提出的自终止栅凹槽刻蚀技术,采用以GaN盖层(CL)作为凹槽掩模的新颖方法论证了常关凹槽栅极的AlGaN / GaN MOSFET,从而简化了器件制造加工并降低了制造成本。 GaN CL可以充当栅极凹进工艺的有效凹进掩模,包括在650°C下热氧化45分钟,然后在70°C的氢氧化钾(KOH)中进行4分钟蚀刻。在栅极凹陷工艺之后,在GaN CL的表面形态,直接在GaN CL上形成的欧姆接触的接触电阻以及二维电子气的薄层电阻方面,没有观察到明显的变化(2- GaN CL下方的DEG)沟道层。所制造的器件具有阈值电压(高达5 V),最大漏极电流(mA / mm),高导通/截止电流比以及低正向栅极漏电流mA / mm。同时,OFF-状态击穿电压(栅漏距离为6 m的器件为450 V.

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号