Impacts of Back Gate Bias Stressing on Device Characteristics for Extremely Thin SoI (ETSoI) MOSFETs

摘要

In this letter, investigations of impacts of back bias stressing on extremely thin SoI MOSFETs with channel thickness varying from 11 to 4 nm are presented. For a given gate length $(L_{G})$, with back bias stressing from ${-}{20}$ to 20 V, drain-induced barrier lowering (DIBL) with small values are obtained due to increment of carrier confinement toward the top gate for pMOSFET. While with enlargement of back bias voltage stressing from ${-}{40}$ to 40 V, the DIBL behaviors are different for channel thickness from 11 to 4 nm. The DIBL with channel thickness of 4 nm is consistent down to small value along with positive gate bias stressing. While for channel thickness of 7 and 11 nm, the DIBL both changes to large values at two ends of voltage stressing. In addition, subthreshold swing gets worse with more positive back gate bias (BGB) stressing. In addition, smaller channel thickness would lead to even more degraded subthreshold swing and poor gate controllability by applying a large BGB stressing. These are mainly due to high electric field in the channel induced by BGB. High positive BGB would lead to an enlargement of depletion width at the channel corner and short channel effect would get worse. In addition, high electric field is bad for channel mobility, which leads to degraded subthreshold swing.