首页> 外文期刊>Electron Device Letters, IEEE >PBTI Investigation of MoS2 n-MOSFET With Al2O3 Gate Dielectric
【24h】

PBTI Investigation of MoS2 n-MOSFET With Al2O3 Gate Dielectric

机译:具有Al2O3栅介质的MoS2 n-MOSFET的PBTI研究

获取原文
获取原文并翻译 | 示例

摘要

For the first time, we report the positive bias temperature instability of the back gated multilayer MoS2 n-MOSFETs with Al2O3 gate dielectric. In the stress phase, the Id-Vg curve shifts to the positive gate bias. In the recovery phase, it shifts back to the negative gate bias. After 5000 s recovery, it completely recovers to that of the fresh device. The results indicate that the voltage shift is solely due to trapping and detrapping of the pre-existing border traps in the Al2O3 dielectric. The traps consist of fast and slow components with the capture time constants of 7 and 1.8 × 102 s and the emission time constants of 15 and 1.0 × 103 s, respectively. The results from first-order trapping and detrapping calculations are in overall agreements with 12 measured AVg curves including six under stress voltages and six in the recovery phases. The energy densities for the fast and slow traps are derived to be in the order of 1013 cm-2 eV-1 above the bottom of the MoS2 conduction band.
机译:我们首次报道了具有Al2O3栅极电介质的背栅多层MoS2 n-MOSFET的正偏置温度不稳定性。在应力阶段,Id-Vg曲线移至正栅极偏置。在恢复阶段,它移回到负栅极偏置。恢复5000秒后,它将完全恢复到新设备的状态。结果表明,电压偏移仅是由于Al2O3电介质中先前存在的边界陷阱的俘获和去俘获。陷阱由快和慢成分组成,捕获时间常数分别为7和1.8×102 s,发射时间常数分别为15和1.0×103 s。一阶俘获和去俘获计算的结果总体上与12条测得的AVg曲线一致,其中包括6条在应力电压下和6条在恢复阶段。快阱和慢阱的能量密度在MoS2导带底部上方大约为1013 cm-2 eV-1。

著录项

  • 来源
    《Electron Device Letters, IEEE》 |2017年第5期|677-680|共4页
  • 作者单位

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

    Department of Electronic Engineering, National Chiao-Tung University, Hsinchu, Taiwan;

    Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Stress; Molybdenum; Sulfur; Logic gates; Stress measurement; Voltage measurement; Electron traps;

    机译:应力;钼;硫;逻辑门;应力测量;电压测量;电子陷阱;

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号