SRAM With Buried Power Distribution to Improve Write Margin and Performance in Advanced Technology Nodes

摘要

This letter proposes for the first time buried powered static random-access memory (SRAM) to achieve enhanced write margin and performance in advanced CMOS technology nodes. The buried power rail (BPR) for SRAM is silicon verified. The BPR helps to lower the bitline and wordline resistance by relaxing metal width in SRAM circuits and thereby enhances the write margin and performance. The proposed SRAM provides up to 340 mV and 30.6% improvement in write margin and read speed, respectively, as compared to its conventional counterpart without incurring any area penalty in a hardware influenced 3 nm CMOS technology.