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Write margin of SRAM cells improved by controlling power supply voltages to the inverters via corresponding bit lines
Write margin of SRAM cells improved by controlling power supply voltages to the inverters via corresponding bit lines
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机译:通过通过相应的位线控制反相器的电源电压,可以改善SRAM单元的写裕度
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摘要
Each memory cell has a pair of inverters whose inputs and outputs are connected to each other and holds complementary data respectively in storage nodes which are outputs of the inverters. In a write operation during which the complementary data are written to the storage nodes respectively, the power control circuit sets a power supply voltage of the inverter having the storage node to which low level is written lower than a power supply voltage of the inverter having the storage node to which high level is written. Since power supply capability to the inverter having the storage node to which the low level is written lowers, the voltage of the storage node easily changes to the low level. That is, a write margin of a memory cell can be improved.
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