Improved Write Margin 6T-SRAM for Low Supply Voltage Applications

摘要

In this paper a new technique to increase the write margin of 6T-SRAM cell is proposed. Using this technique the area of subthreshold SRAM cell is reduced and also the Write cycle is improved significantly with a lower area overhead. In this technique, PMOS stacked network is used to evaluate the write cycle. Based on behavior of devices in 65nm for weak inversion operation, this technique is proposed to decrease area overhead of 6T-SRAM in subthreshold region.