A High-Speed Si-Based Power Transistor With Bipolar-Assisted Gate Discharging Behavior

Lin Min-Zhi; Liu Lei; Ye Zhi-Yuan; Yuan Yuan-Lin; Yao Yao; Wang Peng-Fei

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A High-Speed Si-Based Power Transistor With Bipolar-Assisted Gate Discharging Behavior

机译：具有双极辅助栅极放电行为的高速硅基功率晶体管

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摘要

This letter presentsa novel super junction (SJ) device integrated with an on-chip bipolar junction transistor (BJT) connected between the gate and the source. This parallel path through the BJT to discharge the gate of the SJ device reduces its switch-OFF time by 26%. It also raises the human-body model electro-static discharge failure threshold from 1.5 to 2.3 kV for the same chip size. In addition, gate voltage oscillation during the switch-OFF transient is effectively suppressed.

机译：这封信提出了一种新颖的超结（SJ）器件，该器件与连接在栅极和源极之间的片上双极结晶体管（BJT）集成在一起。通过BJT放电SJ器件栅极的并联路径将其关断时间减少了26％。对于相同的芯片尺寸，它还将人体模型的静电放电失败阈值从1.5 kV提高到2.3 kV。另外，有效地抑制了关断瞬变期间的栅极电压振荡。

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来源
《IEEE Electron Device Letters》 |2019年第4期|589-592|共4页
作者
Lin Min-Zhi; Liu Lei; Ye Zhi-Yuan; Yuan Yuan-Lin; Yao Yao; Wang Peng-Fei;
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作者单位

Fudan Univ, Collaborat Innovat Ctr IC Design & Mfg Yangtze Ri, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China;

Fudan Univ, Collaborat Innovat Ctr IC Design & Mfg Yangtze Ri, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China|Suzhou Oriental Semicond, Device Dept, Suzhou 215123, Peoples R China;

Fudan Univ, Collaborat Innovat Ctr IC Design & Mfg Yangtze Ri, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China;

Suzhou Oriental Semicond, Device Dept, Suzhou 215123, Peoples R China;

Fudan Univ, Collaborat Innovat Ctr IC Design & Mfg Yangtze Ri, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China;

Fudan Univ, Collaborat Innovat Ctr IC Design & Mfg Yangtze Ri, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Super junction; integrated gate driver; turn-OFF time; gate voltage oscillation;

机译：超级交界处;集成栅极驱动器;关闭时间;栅极电压振荡;

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专利

1. A High-Speed Si-Based Power Transistor With Bipolar-Assisted Gate Discharging Behavior [J] . Lin Min-Zhi, Liu Lei, Ye Zhi-Yuan, IEEE Electron Device Letters . 2019,第4期

机译：具有双极辅助栅极放电行为的高速SI基功率晶体管
2. Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance [J] . Sourav Guh, Prithviraj Pachal, Sudipta Ghosh, Superlattices and microstructures . 2020,第Octa期

机译：新型双栅极金属注入堆叠栅极氧化术隧道场效应晶体管（TFET）的分析模型，用于低功耗和高速性能
3. Built-in self test design of power switch with clock-gated charge/discharge transistor [J] . Computers & Digital Techniques, IET . 2014,第2期

机译：具有时钟门控充放电晶体管的电源开关的内置自检设计
4. Quasi-double gate mode for sleep transistors in UTBB FD SOI low-power high-speed applications [C] . Bol David, Kilchytska Valeriya, De Vos Julien, IEEE International SOI Conference. . 2012

机译：UTBB FD SOI低功耗高速应用中睡眠晶体管的准双栅极模式
5. Advanced Insulated-Gate Bipolar Transistors for High-Speed Hard-Switching Applications [D] . Feng, Hao. 2015

机译：高速绝缘栅双极晶体管，用于高速硬开关应用
6. Conformally Gated Surface Conducting Behaviors of Single-Walled Carbon Nanotube Thin-Film-Transistors [O] . Kyung-Tae Kim, Keon Woo Lee, Sanghee Moon, 2021

机译：单壁碳纳米管薄膜晶体管的共形门导电行为
7. Conformally Gated Surface Conducting Behaviors of Single-Walled Carbon Nanotube Thin-Film-Transistors [O] . Kyung-Tae Kim, Keon Woo Lee, Sanghee Moon, 2021

机译：单壁碳纳米管薄膜晶体管的共形门导电行为

A High-Speed Si-Based Power Transistor With Bipolar-Assisted Gate Discharging Behavior

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